1. Field of the Invention
The invention relates to a buffer device and methods for adaptively sharing memory area among a plurality of functions, for example as provided between a transmit buffer and a receive buffer on a communications network switch.
2. Description of the Prior Art
FIG. 1 is a block diagram of an exemplary network switch 10, which includes a network switch fabric 12, six input/output ports 14A-F, and six buffering and control circuits 16A-F. Each buffering and control circuit 16 is coupled between the switch fabric 12 and a corresponding one of the ports 14A-F. A network switch may have any number of ports, and may have its buffering and control functions either centralized, or distributed as shown in FIG. 1. In operation, data is received on one of the ports (e.g., port 14A) and a first corresponding buffering and control circuit (e.g., 16A) routes the communication data through the switch fabric 12 to a second buffering and control circuit (e.g., 16D) and to a second port (e.g., 14D).
FIG. 2 illustrates one known approach of buffering in a portion 20 of a communications network switch. A network port 24 is shown, coupled to the network switch fabric 22 via both receive buffer 26 and transmit buffer 28. Control circuitry for the port 24 is not shown. In this example, buffering for the port 24 is achieved by using physically separate memory devices, one for transmit (28) and the other for receive (26). This approach allows a designer of a network switch to maximize buffering in both transmit and receive directions for a given memory density, and achieve a minimum latency in accessing the data. It does, however, have a drawback in cost and port density--i.e., two buffer devices are required per port on the printed circuit board (PCB), making the PCB design more complex because of the additional real estate requirement, which in turn raises the cost. Another drawback is that when more devices are added for buffering, less room is available for actual network ports on the PCB.
FIG. 3 illustrates another approach to switch buffering for a portion 30 of a network switch, in which a single buffering device 35 is coupled between the network switch fabric 32 and a network port 34. A boundary 38 splitting the memory 34 in half (between transmit 37 and receive 36) is static; the boundary may be predetermined by PCB hardware, or may be predetermined by software. An advantage of this approach (over the design shown in FIG. 2) is that by using only one buffer device per port, the PCB design is simplified, and generally the cost lower. One disadvantage is that buffering is reduced to half of the amount provided by the technique shown in FIG. 2, assuming both designs use the same memory device. Thus, for the single memory device 34 to achieve the same level of buffering as buffers 26 and 28 of FIG. 2, twice as many devices would be needed, eliminating the advantage.
In yet another buffering scheme, a switch includes a mechanism which selects buffering to the predetermined highest load data stream, at the expense of any data stream having a lesser load. For example, it may be predetermined that twice as much receive buffering as transmit buffering, is desirable. Such a design based on the FIG. 2 embodiment would include a memory chip for the receive data that is twice the size of the memory chip used for the transmit data. To achieve the same result from the FIG. 3 embodiment, the boundary 38 would dedicate 2/3 of the device to receive data, and 1/3 to transmit data.
A significant disadvantage results from all of these prior approaches because an individual port in a network switch seldom requires transmit buffering and receive buffering simultaneously. Accordingly, when receive buffering is required, the memory dedicated to transmit buffering represents unused resources. The same is true when transmit buffering is required, but receive buffering is not. Thus, there is a basic inefficiency in the prior art designs.
There is another disadvantage with the switch that weights the buffer towards the direction of the predetermined higher load data stream. Data networks, by their very nature, are extremely non-deterministic, and thus it is difficult to determine what type of traffic will be generated when a device is introduced at a large number of different customer sites. If a memory boundary is placed in a less than optimal position with respect to how the port will utilize the buffer, there is a possibility that memory will be required but unavailable for a data stream in one direction, and memory will be available but not required for a data stream traveling in the other direction.
Thus, a need arises for an improved memory device and method of buffering data.